As is well known, manufacturing yield is a major concern in the high-volume manufacturing of integrated circuit memory devices. A matrix of memory cells often emerges from the manufacturing process in a faulty condition, such that the device will be unsuitable for use. In fact, for the cell matrix taking up most of the device circuit area, the probability of a serious manufacturing fault occurring in the circuit portion occupied by the matrix is quite high. Specifically, in this field of application, the manufacture of non-volatile memory devices of the so-called Flash type shows a comparatively low yield rate.
There have been prior proposals for improving the yield from the manufacturing process of Flash memories. The solution previously adopted provided a circuit-oriented remedy. In essence, the structure of the matrix of memory cells is given additional rows and/or columns, known as redundancy rows/columns, which can be utilized in place of any faulty rows/columns that have developed malfunctions as determined by device testing. The skilled person in the art is familiar with the criteria for designing and utilizing redundancy rows/columns, but is also aware of the limitations of such a circuit-oriented approach.
It is presently expected that continually evolving technology may lead in the near future to processing improvements that will make row redundancy an unnecessary measure. However, no comparable improvements are expected with respect to making column redundancy unnecessary.
As an example, and for an easier understanding of the aspects of this invention, the advantages and drawbacks of column redundancy will be reviewed briefly below, keeping in mind that a primary objective of this technique is to remedy malfunctions brought about by individual cells whose electrical characteristics are different from their design specifications. It is indeed at the designing stage that the ideal number of redundancy columns must be decided upon, as a compromise between the safety level sought and the circuit area increase for the redundancy columns.
It should be considered that most of the circuit feature-size is due to circuitry needed for controlling the inclusion of redundancy columns. Moreover, the size of such control circuitry is bound to increase with the overall size of the memory device. This is explained in that a redundant element must be selected by comparing a memory address outside the device with the contents of a specific internal register whereinto the locations of the columns (or the rows) to be put in exchange are stored.
In the particular instance of Flash memories, wherein the matrix is set up in sectors, column redundancy commands special attention at the design stage. In fact, with the columns being assigned to individual sectors rather than to the device as a whole, it often occurs that: an integrated device must be rejected wherein one sector cannot be repaired due to its supply of redundant elements having been exhausted, while other sectors of the same device may have a surplus of redundant: elements available to them.